&axi_gpio_0 {
    compatible = "generic-uio";
};
axi_gpio_0: gpio@41200000 {
            #gpio-cells = <2>;
            compatible = "xlnx,xps-gpio-1.00.a";
            gpio-controller ;
            reg = <0x41200000 0x10000>;
            xlnx,all-inputs = <0x0>;
            xlnx,all-inputs-2 = <0x0>;
            xlnx,all-outputs = <0x0>;
            xlnx,all-outputs-2 = <0x0>;
            xlnx,dout-default = <0x00000000>;
            xlnx,dout-default-2 = <0x00000000>;
            xlnx,gpio-width = <0x18>;
            xlnx,gpio2-width = <0x20>;
            xlnx,interrupt-present = <0x0>;
            xlnx,is-dual = <0x0>;
            xlnx,tri-default = <0xFFFFFFFF>;
            xlnx,tri-default-2 = <0xFFFFFFFF>;
        };
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <sys/mman.h>
#include <fcntl.h>

#define GPIO_MAP_SIZE 		0x10000
#define GPIO_DATA_OFFSET	0x00
#define GPIO_TRI_OFFSET		0x04
#define GPIO_DATA2_OFFSET	0x08
#define GPIO_TRI2_OFFSET	0x0C
#define GPIO_GLOBAL_IRQ		0x11C
#define GPIO_IRQ_CONTROL	0x128
#define GPIO_IRQ_STATUS		0x120

volatile int counter;

inline void gpio_write(void *gpio_base, unsigned int offset, unsigned int value)
{
	*((volatile unsigned *)(gpio_base + offset)) = value;
}

inline unsigned int gpio_read(void *gpio_base, unsigned int offset)
{
	return *((volatile unsigned *)(gpio_base + offset));
}

unsigned int get_memory_size(char *sysfs_path_file)
{
	FILE *size_fp;
	unsigned int size;

	// open the file that describes the memory range size that is based on the
	// reg property of the node in the device tree

	size_fp = fopen(sysfs_path_file, "r");

	if (!size_fp) {
		printf("unable to open the uio size file\n");
		exit(-1);
	}

	// get the size which is an ASCII string such as 0xXXXXXXXX and then be stop
	// using the file

	fscanf(size_fp, "0x%08X", &size);
	fclose(size_fp);

	return size;
}

void wait_for_interrupt(int fd, void *gpio_ptr)
{
	int pending = 0;
	int reenable = 1;
	unsigned int reg;


	// block on the file waiting for an interrupt */
	read(fd, (void *)&pending, sizeof(int));

	counter = counter + 1;


	// the interrupt occurred for the 1st GPIO channel so clear it
	reg = gpio_read(gpio_ptr, GPIO_IRQ_STATUS);
	if (reg)
		gpio_write(gpio_ptr, GPIO_IRQ_STATUS, 1); //


	// re-enable the interrupt in the interrupt controller thru the
	// the UIO subsystem now that it's been handled

	write(fd, (void *)&reenable, sizeof(int));
	}

int main()
{
	int uio1_fd;
	void *ptr;
	int gpio_size;


	if ((uio1_fd = open("/dev/uio1", O_RDWR)) < 0)
		{
			perror("open uio1");
		}
		else{printf("uio1 opened \n");}

	gpio_size = get_memory_size("/sys/class/uio/uio1/maps/map0/size");

	ptr = mmap(NULL, gpio_size, PROT_READ|PROT_WRITE, MAP_SHARED, uio1_fd, 0);

	if (ptr == MAP_FAILED) {
			printf("Mmap call failure.\n");
			return -1;
		}
	gpio_write(ptr, GPIO_TRI_OFFSET, 0xFF); // GPIO Channel 1 input

	gpio_write(ptr, GPIO_GLOBAL_IRQ, 0x80000000); // GIER, 31. Bit
	gpio_write(ptr, GPIO_IRQ_CONTROL, 1);  // Channel 1 Interrupt enable

	//wait for interrupt
	while(1)
	{
		wait_for_interrupt(uio1_fd, ptr);
		printf("Interrupt: %d", counter);
		puts("");
	}


	munmap(ptr, gpio_size);

	return 0;
}


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system-top.dtsi 에다가 하기 내용 추가


/{

    axi_radar: axi_radar@41200000 {

        compatible ="xlnx,axi-radar";

        reg = <0x41200000 0x10000>;

    };

};


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주요 부분


#define DRIVER_NAME "axi-radar"

#define DEVICE_NAME "axi-radar"

#define CLASS_NAME  "axiRadarClass"


/* Simple example of how to receive command line parameters to your module.

   Delete if you don't need them */

unsigned myint = 0xdeadbeef;

char *mystr = "default";


/* class */

static struct class* axiRadarClass = NULL;

static struct device* axiRadarDevice = NULL;


...



static int __init axi_radar_init(void)

{   

    printk("<1>AXI-Radar. 1\n");

    printk("<1>Module parameters were (0x%08x) and \"%s\"\n", myint, mystr);

    

    radar_base_vaddr = 0x00;

    majorNumber = register_chrdev(0, DEVICE_NAME, &fops);

    if (majorNumber< 0) { 

        printk(KERN_ALERT "axi-radar : Registering char device failed with %d\n", majorNumber); 

        return majorNumber;

    } 

    printk(KERN_INFO "axi-radar : major number %d.\n", majorNumber);

    

    axiRadarClass = class_create(THIS_MODULE, CLASS_NAME);

    if (IS_ERR(axiRadarClass)){                // Check for error and clean up if there is

        unregister_chrdev(majorNumber, DEVICE_NAME);

        printk(KERN_ALERT "axi-radar : Failed to register device class\n");

        return PTR_ERR(axiRadarClass);          // Correct way to return an error on a pointer

    }

    printk(KERN_INFO "axi-radar : device class registered correctly\n");

    

    // Register the device driver

    axiRadarDevice = device_create(axiRadarClass, NULL, MKDEV(majorNumber, 0), NULL, DEVICE_NAME);

    if (IS_ERR(axiRadarDevice)){               // Clean up if there is an error

        class_destroy(axiRadarClass);           // Repeated code but the alternative is goto statements

        unregister_chrdev(majorNumber, DEVICE_NAME);

        printk(KERN_ALERT "axi-radar : Failed to create the device\n");

        return PTR_ERR(axiRadarDevice);

    }

    

    return platform_driver_register(&axi_radar_driver);

}



static void __exit axi_radar_exit(void)

{

    device_destroy(axiRadarClass, MKDEV(majorNumber, 0));     // remove the device

    class_unregister(axiRadarClass);                          // unregister the device class

    class_destroy(axiRadarClass);                             // remove the device class

    unregister_chrdev(majorNumber, DEVICE_NAME);             // unregister the major number


    platform_driver_unregister(&axi_radar_driver);

    printk(KERN_ALERT "axi-radar : exit.\n");

}



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1. Kernel Update


U-Boot-PetaLinux> setenv ipaddr 192.168.0.125;setenv serverip 192.168.0.43;tftpboot 0x1000000 image.ub

U-Boot-PetaLinux> sf probe 0 0 0

U-Boot-PetaLinux> sf erase 0x1000000 0x1000000

U-Boot-PetaLinux> sf write 0x1000000 0x1000000 0xffffff



2. Kernel Boot Script


U-Boot-PetaLinux> sf probe 0 0 0

U-Boot-PetaLinux> sf read 0x8000000 0x1000000 0x1000000

U-Boot-PetaLinux> bootm 0x8000000


U-Boot-PetaLinux> setenv bootcmd 'sf probe 0 0 0; sf read 0x8000000 0x1000000 0x1000000; bootm 0x8000000'



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1. Vivado에서 SDHCI 블럭 Disable 하고 UART0블럭 Enable

  UART0 RX MIO 42

  UART0 TX MIO 43



2. Vivado - Synth - Implement - Export Hardware ... 순서대로 진행



3. U-Boot 다시 빌드



4. DTSI 수정


~/Xilinx-ZC706-2016.3/subsystems/linux/configs/device-tree/system-top.dts 파일 하기 부분 추가

&uart0 {

    status = "okay";

};


&sdhci0 {

    status = "disabled";

};


&sdhci1 {

    status = "disabled";

};



5. system-cont.dtsi 파일에서 하기 부분 추가


 aliases {

        serial0 = &uart1;

        serial1 = &uart0;

        ethernet0 = &gem0;

        spi0 = &qspi;

    };



6. 컴파일

petalinux-build -c device-tree 

petalinux-package --image

cp images/linux/image.ub /tftpboot/



7. 확인 방법

U-boot에서 fdt를 사용한다.

fdt addr 0x868c7dc

fdt print


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1. ~/Xilinx-ZC706-2016.3/subsystems/linux/configs/u-boot/config 파일에서 


# CONFIG_CMD_MMC is not set

# CONFIG_ZYNQ_SDHCI is not set



2. platform-auto.h에서


/* sdio - ps7_sd_0 */

#if 0

#define CONFIG_ZYNQ_SDHCI0  0xE0100000

#define CONFIG_MMC

#define CONFIG_GENERIC_MMC

#define CONFIG_SDHCI

#define CONFIG_SUPPORT_VFAT

#define CONFIG_DOS_PARTITION

#define CONFIG_FAT_WRITE

#define CONFIG_ZYNQ_SDHCI_MAX_FREQ  52000000

#endif



3. ReBuild


#!/bin/bash


petalinux-build -c u-boot


petalinux-package --boot --fsbl /home/shlee/shlee_zc706/shlee_zc706.sdk/shlee_zc706_fsbl/Debug/shlee_zc706_fsbl.elf --fpga /home/shlee/shlee_zc706/shlee_zc706.runs/impl_1/designz_main_wrapper.bit --uboot --force -o images/linux/BOOT.BIN


cp images/linux/BOOT.BIN /tftpboot

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1. petalinux 확인
shlee@xilinxdev:~$ echo $PETALINUX
/opt/petalinux
shlee@xilinxdev:~$ 


2.프로젝트 생성
shlee@xilinxdev:~$ petalinux-create -t project -s /opt/petalinux/Xilinx-ZC706-v2016.3-final.bsp 
INFO: Create project: 
INFO: Projects: 
INFO:   * Xilinx-ZC706-2016.3
INFO: has been successfully installed to /home/shlee/
INFO: New project successfully created in /home/shlee/



3. 전체 빌드
shlee@xilinxdev:~/Xilinx-ZC706-2016.3$ petalinux-build
INFO: Checking component...
INFO: Generating make files and build linux
INFO: Generating make files for the subcomponents of linux
...
...


4. 커널 빌드
shlee@xilinxdev:~/Xilinx-ZC706-2016.3$ petalinux-build -c kernel
INFO: Checking component...
INFO: Generating make files and build linux/kernel
INFO: Generating make files for the subcomponents of linux/kernel
INFO: Building linux/kernel
[INFO ] build linux/kernel
...

shlee@xilinxdev:~/Xilinx-ZC706-2016.3$ petalinux-build -x package
INFO: Checking component...
INFO: Generating make files and build linux
INFO: Generating make files for the subcomponents of linux
INFO: Building linux
[INFO ] package rootfs.cpio to /home/shlee/Xilinx-ZC706-2016.3/images/linux
[INFO ] Update and install vmlinux image
...


5. 모듈 추가
shlee@xilinxdev:~/Xilinx-ZC706-2016.3$ petalinux-create -t modules --name axi-gpio --enable 

~/Xilinx-ZC706-2016.3/components/modules/axi-gpio가 생성되어있음

모듈 컴파일
shlee@xilinxdev:~/Xilinx-ZC706-2016.3$ petalinux-build -c rootfs/axi-gpio -x install


6.  패키지 생성
shlee@xilinxdev:~/Xilinx-ZC706-2016.3$ petalinux-build -x package


7. image.ub 생성
shlee@xilinxdev:~/Xilinx-ZC706-2016.3$ petalinux-package --image


8. scp 파일전송
scp axi-gpio.ko root@192.168.0.52:/home/root 


9. u-boot 빌드

$ petalinux-build -c u-boot



10. u-boot 패키지 (BOOT.BIN 만들기)

$ petalinux-package --boot --fsbl pre-built/linux/images/zynq_fsbl.elf --fpga pre-built/linux/implementation/download.bit --uboot --force -o images/linux/BOOT.BIN



11. u-boot에서 BOOT.BIN QSPI에 Writing 하기

U-Boot-PetaLinux> setenv ipaddr 192.168.0.125;setenv serverip 192.168.0.43; tftpboot 0x1000000 BOOT.BIN;sf probe 0 0 0;sf erase 0x0 0x1000000;sf write 0x1000000 0x0 0xffffff;reset



12. u-boot에서 네트웍으로 리눅스 부팅

U-Boot-PetaLinux> setenv ipaddr 192.168.0.125;setenv serverip 192.168.0.43;tftpboot 0x8000000 image.ub;bootm 0x8000000



13. u-boot에 I2C 추가


~/build/Xilinx-ZC706-2016.3/subsystems/linux/configs/u-boot/platform-auto.h 파일


#define CONFIG_SYS_I2C_ZYNQ


/* I2C */

#if defined(CONFIG_SYS_I2C_ZYNQ)


# define CONFIG_ZYNQ_I2C0

# define CONFIG_SYS_I2C

# define CONFIG_CMD_I2C

# define CONFIG_SYS_I2C_ZYNQ_SPEED              100000

# define CONFIG_SYS_I2C_ZYNQ_SLAVE              0

#endif



14. u-boot 에 새로운 fsbl 적용하기


#!/bin/bash

petalinux-build -c u-boot

petalinux-package --boot --fsbl /home/shlee/shlee_zc706/shlee_zc706.sdk/shlee_zc706_fsbl/Debug/shlee_zc706_fsbl.elf --fpga /home/shlee/shlee_zc706/shlee_zc706.runs/impl_1/designz_main_wrapper.bit --uboot --force -o images/linux/BOOT.BIN





1. petalinux-build 한 images 파일을 sdk에 적절한 폴더에 옮김


2. Xilinx SDK에 [Xilinx Tools]-[Create Zynq Boot Image]를 선택

 


요렇게 넣고


3. 

xsdb% targets

xsdb% source D:\\vivado_work\\zc706_test1\\zc706_test1\\zc706_test1.sdk\\design_1_wrapper_hw_platform_0\\ps7_init.tcl

xsdb% ps7_init

xsdb% ps7_post_config

xsdb% dow D:\\vivado_work\\zc706_test1\\zc706_test1\\zc706_test1.sdk\\linux_image_test\\u-boot.elf

xsdb% dow -data D:\\vivado_work\\zc706_test1\\zc706_test1\\zc706_test1.sdk\\linux_image_test\\BOOT.bin 0x08000000

xsdb% con


4. U-boot가 부팅되면

> sf probe 0 0 0

> sf erase 0x0 0x01000000

> sf write 0x08000000 0 0xffffff


5. 딥스위치 4번 High로 올려도 U-boot 부팅됨....





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ZC706 Doesn't work with VADJ at 1.8v  (0) 2016.11.07

1. petalinux-v2015.4-final-installer-dec.run 다운로드 설치

/opt/pkg에다가


2. Xilinx-ZC706-v2015.4-final.bsp 다운로드 설치

/opt/pkg/petalinux-/ 에 다가


3. sudo dpkg-reconfigure dash <No> 선택


4. petalinux-create -t project -s <BSP>


5. cd <BSP>

   petalinux-build 


 

참조:

http://engineernote.hatenablog.com/entry/2016/01/31/012227



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https://forums.xilinx.com/t5/Xilinx-Boards-and-Kits/ZC706-Doesn-t-work-with-VADJ-at-1-8v/td-p/430086




ZC706 Doesn't work with VADJ at 1.8v

 Accepted Solution SOLVED
Observer
teqdruid
Posts: 20
Registered: ‎03-11-2014
Accepted Solution 

ZC706 Doesn't work with VADJ at 1.8v

Hello Everyone-

 

Has anyone successfully used their ZC706 with VADJ set to 1.8v?

 

I've used TI's Fusion Digital Power Designer to set the UCD90120A @ Address 101d Rail #4 to 1.8v. Rail #4 appears to be VADJ based on the ZC706 schematic and the fact that it was the only one initially set to 2.5v. I'm about to run out for a voltmeter to verify, but I'm 80% sure this is correct.

 

After adjusting VADJ to 1.8v, lots of stuff stopped working. The fan, the I2C RTC (and possibly all the I2C chips -- the kernel just complains about this one), and -- most importantly -- the ENTIRE PL REGION! Whenever any software (either the FSBL or u-boot) try to communicate with the PL to get info about it or upload a bitstream, they get invalid responses and hang. So it seems like VADJ is being used as a core voltage for the FPGA and perhaps a few SoC peripherials.

 

So am I doing something incredibly stupid? Any suggestions?

 

Thanks in advance,

John


Accepted Solutions
Observer
teqdruid
Posts: 20
Registered: ‎03-11-2014
 

Re: ZC706 Doesn't work with VADJ at 1.8v

OK... I finally figured this out. It's my mistake, but in my defense the documentation is clear as mud.

 

For anyone who sees this in the future (including myself):

Unlike on the ZC702, simply programming the Vout of the UCD90120A Rail #4 is not enough. I think this is merely the voltage which it is monitoring, it does not instruct the actual regulator -- a TPS84621 -- what voltage to put out. To actually set the output voltage to 1.8, 2.5 or 3.3v, you must change the output of UCD90120A pins 33 and 36, as per page 53 of the zc706 schematic. Without those settings, the UCD90120A will observe an over-voltage condition and shut down Vadj

altogether. I had assumed that the UCD90120A knew this and would set those outputs automatically. It doesn't!

 

To the Xilinx folks:

Please add _explicit_ instructions for modifying Vadj to UG954 in the "ZC706 Board Powqer System" section, even if those instructions assume the user has a TI USB Interface Adapter and the TI Fusion software. That's a paragraph which would have saved me a couple of days.

 

~John 

 

View solution in original post


All Replies
Moderator
umamahe
Posts: 1,766
Registered: ‎08-01-2012

Re: ZC706 Doesn't work with VADJ at 1.8v

The ZC706 supports 1.8V on VADJ.  Care needs to be taken when adjusting VADJ to make sure voltage thresholds are not violated and hardware is not damaged.

Customers can work with TI Support to create the script needed to change the VADJ value.

 

Supported ranges of VADJ which is 1.8V, 2.5V, and 3.3V.  The general rule is if you go below 1.8V, then you might lose some other functionality in the board.  VADJ will be fine, but other things on the board may not work (i.e. HDMI, AMS-101, level shifters, etc.)

 

In your case VADJ might adjected just below 1.8V

________________________________________________

Please mark this post as an "Accept as solution" in case if it helped to resolve your query. So that it will help to other forum users to directly refer to the answer.

Give kudos to this post in case if you think the information is useful and reply oriented.

Observer
teqdruid
Posts: 20
Registered: ‎03-11-2014
 

Re: ZC706 Doesn't work with VADJ at 1.8v

OK... I finally figured this out. It's my mistake, but in my defense the documentation is clear as mud.

 

For anyone who sees this in the future (including myself):

Unlike on the ZC702, simply programming the Vout of the UCD90120A Rail #4 is not enough. I think this is merely the voltage which it is monitoring, it does not instruct the actual regulator -- a TPS84621 -- what voltage to put out. To actually set the output voltage to 1.8, 2.5 or 3.3v, you must change the output of UCD90120A pins 33 and 36, as per page 53 of the zc706 schematic. Without those settings, the UCD90120A will observe an over-voltage condition and shut down Vadj

altogether. I had assumed that the UCD90120A knew this and would set those outputs automatically. It doesn't!

 

To the Xilinx folks:

Please add _explicit_ instructions for modifying Vadj to UG954 in the "ZC706 Board Powqer System" section, even if those instructions assume the user has a TI USB Interface Adapter and the TI Fusion software. That's a paragraph which would have saved me a couple of days.

 

~John 

 

Participant
eng_karim
Posts: 62
Registered: ‎07-15-2013

Re: ZC706 Doesn't work with VADJ at 1.8v

Hi All,

 

When I connected the Ti Fusion the fan stops working so I thought this is a sign of some other consequences

I am sorry but I didn't get the idea of the solution written or how to do it so please if someone can mention the steps more clearly 

also I found these slides but I don't know if they are related to the problem or not (see the attachment)

 

I am bit afraid to do some unaware changes that may damage the board

 

Thanks

Karim

 

 

Participant
eng_karim
Posts: 62
Registered: ‎07-15-2013

Re: ZC706 Doesn't work with VADJ at 1.8v

The attachment is about ZC706 Power controllers Reprogramming steps


http://www.xilinx.com/Attachment/ZC706_Power_Controllers_Reprogramming_Steps.pdf

Participant
eng_karim
Posts: 62
Registered: ‎07-15-2013

Re: ZC706 Doesn't work with VADJ at 1.8v

I found the solution so I will write it for the others and to thank the people who are searching for a solution

My problem was simply that when I plug the TI Fusion usb to the PMBus into my Zynq 706 board the fan is not working and actually to be more precise there is no Vadj input to the circuit and this could be clearly noticed from the Vadj leds on the board where they were switched off

 

the solution that I found and it works with me is in the following link

http://www.xilinx.com/support/answers/55805.html

 

and briefly you need to updated the firmware of the TI Fusion Software

1) I installed the TI software version 1.9.78

2) Start button, go to All Programs -> Texas Instruments Fusion Digital Power Designer > Tools USB Adapter Firmware Download Tool.

then I discovered that my firmware is 1.0.11 and I need to updated to 1.0.14

3) choose "select USB Adapter firmware" and choose version 1.0.14 then it will be downloaded and installed then unplug plug the USB cable and it works fine

 

it is better to mention that I didn't need to go through the steps I mentioned in the pdf in the previous post or even to change the voltage levels of the board and I don't know if it benefits in other cases

Thanks

Karim

Visitor
nvijendran
Posts: 3
Registered: ‎07-30-2015

Re: ZC706 Doesn't work with VADJ at 1.8v

UCD90120A - registers

VOUT_OV_FAULT_LIMIT (command byte – 0x40) – over voltage fault limit

VOUT_UV_FAULT_LIMIT (command byte 0x44) – under voltage fault limit

 

By default, VOUT_OV_FAULT_LIMIT was set to 2.875V which is 2.5V + 15%

              and  VOUT_UV_FAULT_LIMIT was set to 2.125 which is 2.5V – 15%

 

The moment, the GPIO19 set to ‘1’, it brings VDAJ with 1.8V which out of range of 2.125 to 2.875.

Hence the VADJ will be shut-off. So it is important to bring down the VOUT_UV_FAULT_LIMIT first, then configure the VADJ to 1.8V and then change the VOUT_OV_FAULT_LIMIT.

 

Here is the procedure to set 1.8V.

  • Select UCD90120 chip in I2C MUX

           i2c send 0x74 0x80

  • Select page3 (rail4)

         i2c write 0x65 0x00 0x03

 

  • Set VOUT_UV_FAULT_LIMIT to 1.53 (1.8 – (15%  of 1.8))

              0x30F6 * 2^(-13)  = 1.53

            i2c write 0x65 0x44 0xF6 0x30          (LSB first)

 

  • Set VADJ to 1.8V

            i2c write 0x65 0xFA 0x0F         (select tck_gpio_19)

           i2c write 0x65 0xFB 0x07         (write value ‘1’)

 

  • Now bring down the VOUT_OV_FAULT_LIMIT to 2.07V (1.8 + (15% fof 1.8))

             0x423E * 2^(-13) = 2.07V

            i2c write 0x65 0x44 0x3E 0x42

  • Issue the command to store above changes permanently

          i2c  send 0x65 0x11     

 

Now even after power cycling the board, the VADJ will be energized with 1.8V.

 

It is important to note that above values are derived from the VOUT_MODE (5-bit 2’s complement integer) = 0x13 = -13 decimal.

One should read their board’s VOUT_MODE first and derive other values.

 

 

Note1: The above I2C design is AXI_IIC core implemented in Zynq-PL.

 

Note2: The VADJ can be measured at pin no 5 / 6 / 7 / 8 of SW12 switch.

Newbie
heitinki
Posts: 1
Registered: ‎08-18-2015

Re: ZC706 Doesn't work with VADJ at 1.8v

I have been trying to get the VADJ to 1.8V using i2c and your example is very close what I was doing. My board always went to cut-off. What I did differently was:

 

1. I did not adjust the VOUT_OV_FAULT_LIMIT

2. I had to set the VOUT_MODE (0x20) manually because using Vivado version 14.4, the repeated start option is removed from the I2C peripheral (look in xiicps.h). This means it is impossible to read any of the UCD90120A register values because I believe the PMBUS/I2C requires repeated start since you first give the write command followed by the repeated start and then the read command. At least I could not get it working. Note! For writing I was using the XIicPs_MasterSendPolled command, which the UCD90120a ACKs. (You can probe it from the J4 PMBUS connector pin10 on the ZC706 board, which is the SDA line. The pin is the top-left one if the board is facing you so that the texts are upright. After each sent byte this line is getting pulled low by the ucd90120a) So basically I knew that what I was writing were actually going in there and getting received.

3. Setting the voltages were different because the VOUT_MODE was different (I probably did it wrong since I was simply trying to put the exponent to 2^-1 so that my under voltage would be at 1.5 ( 3 * 2^-1)

 

So my setting for under voltage was:

i2c write: 0x65 0x44 0x03 0x00

and VOUT_MODE:

i2c write: 0x65 0x20 0x1F (0x1F should correspond to -1 since VOUT_MODE is 8 bits, top 3 bits are reserved and the bottom 5 determine the exponent as two's complement value)

 

These did not work!

 

I adjusted the code that I would write the vout_mode so that it would be -13 as in your example.

(0x65 0x20 0x13) (coincidentally -13 decimal corresponds 0x13 in two's complement with 5 bits 0x00010011)

 

 

 

 

So I included setting  first the UV, then the tck_gpio_19 and last OV voltage in a way that my exponent from VOUT_MODE would be -13 and followed exactly your example but still the board goes into cut-off. When I probe the VADJ value from SW12 it reads about 0.4 volts. Bummer.

 

But I believe that your example is probably the most closest to the truth getting the VADJ programmed to 1.8V. I've read probably all of the threads considering this topic and the ucd90xxx and pmbus reference manuals through multiple times and this really should work.

 

I don't know if you are actually required to use some additional xml scripts that were mentioned here:

http://www.xilinx.com/support/answers/53599.html

 

But yeah, I thank you very much for your effort and posting the instructions, I will probably try to see if I have some small mistake that causes this program not to work properly ( I did not probe the J4 connector for ACKs after using your code) But the c-code runs thru nicely and then cuts the power off.

 

Newbie
john.gwynne
Posts: 2
Registered: ‎07-20-2016

Re: ZC706 Doesn't work with VADJ at 1.8v

Just a quick note that may help others... this is a variation of the above.

 

With the i2c0 bus enabled in the zynq7-ps and on pins MIO50 & 51, the Linux kernel should recognize the i2c controller and the mux.  You should see the bus with the UCD90120A controller as  /dev/i2c-8.  With the i2c-tools installed, the following commands at the shell prompt will change Vadj to 1.8V. (values from above; corrected typing error of OV address from 0x44 to 0x40).

 

[root@zynq ~]# i2cset -y 8 0x65 0x00 0x03
[root@zynq ~]# i2cset -y 8 0x65 0x44 0x30f6 w
[root@zynq ~]# i2cset -y 8 0x65 0xfa 0x0f
[root@zynq ~]# i2cset -y 8 0x65 0xfb 0x07
[root@zynq ~]# i2cset -y 8 0x65 0x40 0x423e w
[root@zynq ~]# i2cset -y 8 0x65 0x11 c

 

Newbie
john.gwynne
Posts: 2
Registered: ‎07-20-2016

Re: ZC706 Doesn't work with VADJ at 1.8v

 

FMC pg_c2m is controlled by the UCD90120A GPIO10.  Registers POWER_GOOD_ON/OFF should also be changed.  You may also want to change the warning thresholds too.

 

[root@zynq ~]# i2cset -y 8 0x65 0x5e 0x33d7 w
[root@zynq ~]# i2cset -y 8 0x65 0x5f 0x30f6 w


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